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Development of Multi-Core Video Decoding Platforms based on High-Level Architecture Simulations, JSC

by Florian Seitner, Michael Bleyer, Margrit Gelautz

Abstract

The high computational demands of state-of-the-art video coding standards such as H.264 pose serious challenges on strongly resource-restricted architectures. For reaching the performance specifications, specialized multi-core architectures for video processing are becoming more and more popular. In this work, we introduce an high-level simulator for supporting the development of such decoding platforms. Our system combines all available information such as hardware measurements, profilings and human expertise. Based on this input, the behaviour of the final architecture running a parallel video decoder is estimated. Using this information, adaptations of the current hardware or software design can be done. The simulator shall aid in developing efficient and application-optimized decoding systems.

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Details

Development of Multi-Core Video Decoding Platforms based on High-Level Architecture Simulations, JSC
TR Number:	TR-188-2-2008-16
First Published:	2008
Publishing History:	Proc. of the Junior Scientist Conference 2008, Vienna; 16.11.2008 - 18.11.2008; ISBN: 978-3-200-01612-5; pages 71 - 72.
Keywords:	Multimedia, Processor, SoC, Video, Decoding, H.264, Multi-Core DSP

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